1. Field of the Invention
The present invention relates to a memory control method and related device, and more particularly, to a memory control method and circuit capable of enhancing buffering performance.
2. Description of the Prior Art
According to new encoding algorithms, encoded data of a frame may be located in another frame due to considerations of output buffering control and bit rate. For example, according to MPEG audio layer 3 (MP3) frame structure, a frame header of a frame includes MP3 side information within the frame, but encoded data of the frame may be located within the preceding frame. In another example, according to Ogg page structure, which is a developing specification, a page header of a page may introduce a plurality of packets coming after. The last packet of the page may include a portion of packet data packed within the page due to reasons such as buffer size limit and bit rate control. The unpacked portion of the packet data may be further packed as a continued packet next to a page header of the next page. It is a common problem of the above-mentioned algorithms, the MP3 frame structure and the Ogg page structure, that encoded data of the same frame or the same page are divided into two portions because of the header between two adjacent frames or pages. As a result, decoding encoded data that is not arranged continuously is not easy as decoding encoded data that is arranged continuously.
FIG. 1 illustrates a buffering control method for a decoding process according to the prior art, wherein Fi denotes an Ith frame, Fi−1 denotes an (I−1)th frame, and so forth. A header Hi, data Di1, Di2, and the frame Fi stored in a buffering region B11 have the same superscript i, representing that the header Hi and the data Di1, Di2 logically belong to the frame Fi. Additionally, the subscripts 1, 2 of the data Di1, Di2 represent two portions 1, 2 of the data Di, which includes the data Di1, Di2, divided by the header Hi between the two adjacent frames Fi, Fi−1. Regarding to the above-mentioned problem that the encoded data is not arranged continuously, the buffering control method shown in FIG. 1 further allocates another buffering region B12, in contrast to the region B11, for storing a bit stream needing to be decoded. According to the buffering control method shown in FIG. 1, the data Di1, Di2 are copied to the buffering region B12 to form within the buffering region B12 continuously arranged data Di1, Di2 for further decoding. As the buffering control method shown in FIG. 1 further allocates the additional buffering region B12, the storage volume requirement of the memory is increased, even if the buffering regions B11, B12 are allocated within the same memory. FIG. 2 illustrates another buffering control method according to the prior art. The buffering control method shown in FIG. 2 parses a data flow read from a disk 205 and respectively store headers Hi−1, Hi, . . . and data Di−11, Di−12, Di1, Di2, . . . in buffering regions B21, B22. Regarding to some embedded systems, it is inconvenient to implement the buffering control method shown in FIG. 2. Both methods of FIG. 1, 2 are imperfect.